Abstract: An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the delay amount storage table into a plurality of regions and selects a region from the plurality of divided regions, a reference signal delay circuit that delays a reference signal according to a test condition stored in a region of the delay amount storage table selected by the offset address generation circuit, and a test waveform formation circuit that generates a test waveform according to the test pattern stored in the test pattern storage circuit and the reference signal delayed by the reference signal delay circuit.