Abstract: A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.

Abstract: A digital signal processor according to the present invention comprises a data bus, a control line for supplying a pre-charge signal at the beginning of each cycle, a first memory for providing a first data stored in a first address to the data bus at a first cycle, for receiving the first data from the data bus and storing the first data in a second address at a second cycle successively with the first cycle, a second memory for storing a second a data, an arithmetic circuit coupled to the data bus and the second memory, for receiving the first and second data at the first cycle, for performing arithmetic operation and producing a result data in response to the first data and second data at the second cycle, a pre-charge circuit for providing a potential to the data bus in response to the pre-charge signal, a pre-charge control circuit for transferring the pre-charge signal to the pre-charge circuit at the first cycle, and for inhibiting the transfer of the pre-charge signal at the second cycle.