Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Abstract: A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.

Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: By using, as a model expression, an expression showing an inverse proportion between a change rate ?Idsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.

Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Abstract: A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.

Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: A circuit simulation apparatus and a modeling method are provided which are useful to design an integrated circuit in a very fine manner by forming a model of such a transistor that widths of element isolating-purpose insulating films are different from each other. In an isolation width depending parameter correcting means 4 of the present invention, an approximate expression of a parameter having an element isolating-purpose insulating film width depending characteristic is formed, and a value of a corrected parameter obtained by employing the formed approximate expression is replaced by a value of an original parameter, so that a transistor model of such a transistor is formed in which element isolating-purpose insulating film widths are different from each other. As a consequence, circuit simulation can be carried out in high precision by considering a change in transistor characteristics caused by a stress, which are approximated to actually measured data.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: In an inventive circuit simulation method, simulation is performed utilizing a circuit simulator, based on a netlist prepared using mask layout data for a circuit, and parameters obtained from measurement data concerning the characteristic of each transistor. The parameters are extracted from the measurement data based on not only the transistor size but also a stress applied to the transistor. Therefore, the circuit simulation can be performed with precision and accuracy never before possible, in consideration of a change in the characteristic of the transistor which is caused by the stress applied thereto.

Abstract: The data transmission method employs IEEE P1394 protocol. The data header of the transmitted isochronous packet is added with a node identifier identifying the transmitter node, so that the receiver node can immediately identify the transmitter node, and can thereby request the transmitter node to maintain transmission. A Broadcast channel is a default channel used for isochronous packet transmission, unless a different channel number is otherwise specified. Thus, it is not necessary for the user to coordinate the channel number used by the transmitting and receiver nodes. It is also not necessary for the transmitter node to notify the receiver node, or the receiver node to notify the transmitter node, of the channel number used.