Abstract: A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.

Abstract: A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.

Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure over the semiconductor substrate, the multilevel wiring structure including a first insulating layer, a first conductive layer on the first insulating layer, a second conductive layer on the first insulating layer, a third conductive layer on the first and second conductive layer, a fourth conductive layer on the third conductive layer, and a second insulating layer on the fourth conductive layer. The multilevel wiring structure includes: a first gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and first, third and fourth conductive films in the first, third and fourth conductive layers, respectively; and a second gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and second, third and fourth conductive films in the second, third and fourth conductive layers, respectively.

Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure over the semiconductor substrate, the multilevel wiring structure including a first insulating layer, a first conductive layer on the first insulating layer, a second conductive layer on the first insulating layer, a third conductive layer on the first and second conductive layer, a fourth conductive layer on the third conductive layer, and a second insulating layer on the fourth conductive layer. The multilevel wiring structure includes: a first gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and first, third and fourth conductive films in the first, third and fourth conductive layers, respectively; and a second gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and second, third and fourth conductive films in the second, third and fourth conductive layers, respectively.

Abstract: A semiconductor device which is provided with: a gate insulating film which contains a high dielectric constant insulating material and has a first width; a lower gate electrode which has a second width that is narrower than the first width; an upper gate electrode which has a third width; and a first spacer layer which covers the lateral part of the upper gate electrode, a part of the lower part of the upper gate electrode, a part of the lower gate electrode, a part of the upper surface of the gate insulating film, said part of the upper surface being out of contact with the lower gate electrode, and the lateral surface of the gate insulating film.