Abstract: The present invention discloses a fluid cooling assembly which facilitates turbulent flow inside the assembly so as to achieve better heat dissipating effect. The cooling assembly comprises an enclosed chamber with an inlet and an outlet for fluid to pass through; together with a heat spreader; a plurality of micropillars and a plurality of heat dissipating fins installed inside the assembly. When fluid flows through the chamber, these elements in combination are adapted to create an enhanced turbulent flow upon the fluid so as to effectively dissipate heat from said heat spreader through the fluid.

Abstract: The present invention discloses a fluid cooling assembly which facilitates turbulent flow inside the assembly so as to achieve better heat dissipating effect. The cooling assembly comprises an enclosed chamber with an inlet and an outlet for fluid to pass through; together with a heat spreader; a plurality of micropillars and a plurality of heat dissipating fins installed inside the assembly. When fluid flows through the chamber, these elements in combination are adapted to create an enhanced turbulent flow upon the fluid so as to effectively dissipate heat from said heat spreader through the fluid.

Abstract: The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Abstract: This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching.

Abstract: The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.

Abstract: The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Abstract: This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching.

Abstract: An electronic or micromechanical device having first (11) and second (12) surfaces and a via extending through the device from the first surface to the second surface. The via comprises integrally formed first (84, 86), second (82) and third (88) portions. The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a part of the first surface (11) of the device. The third portion (88) extends over a part of the second surface (12) of the device. Preferably the first portion comprises first and second parts, the second part extending through an active region of the device and having a narrower width than the first part. A method of forming and filling the via is also disclosed.

Abstract: The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.

Abstract: An electronic or micromechanical device having first (11) and second (12) surfaces and a via extending through the device from the first surface to the second surface. The via comprises integrally formed first (84, 86), second (82) and third (88) portions. The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a part of the first surface (11) of the device. The third portion (88) extends over a part of the second surface (12) of the device. Preferably the first portion comprises first and second parts, the second part extending through an active region of the device and having a narrower width than the first part. A method of forming and filling the via is also disclosed.