Abstract: Adaptive Finite Impulse Response Filter control includes structure and steps for receiving an input signal, filtering the input signal with an FIR filter having a plurality of filter stages, and delaying application of the input signal to at least one of said filter stages with respect to the other filter stages to skip filtering a portion of the input signal.

Abstract: A Finite Impulse Response (FIR) filter is provided including a coefficient generator to generate first and second coefficients, a first control conductor, and a second control conductor. A controller is coupled to a first end of the first control conductor and a first end of the second control conductor. A shared wiring is provided having its first end coupled to the coefficient generator. A first memory is coupled to a second end of the shared wiring and coupled to a second end of the first control conductor to store the first coefficient in response to the controller. A first multiplier is responsive to the first coefficient stored in the first memory and the input, and a first delay circuit is responsive to an input.

Abstract: A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.