Patents by Inventor Yatao Takesue

Yatao Takesue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4802164
    Abstract: A testing method and apparatus for a multi-processor system including a plurality of processors and a plurality of peripheral devices such as input/output (I/O) devices are disclosed. The processors can parallely access specified I/O devices. The apparatus comprises a plurality of I/O control tables each coupled to each of the I/O devices, and storing status information of the (I/O) device, and a scheduler for controlling accessing between the plurality of processors and the plurality of I/O devices. A lock control flag indicating whether each of the I/O devices is locked by one of the processors or not, is set in the respective I/O control table. The scheduler arbitrarily selects a processor which is accessible to an unaccessed I/O device on the basis of the state of the lock control flag of the I/O control table, each time of starting of the I/O device. Then, each time of starting of the I/O device.
    Type: Grant
    Filed: January 6, 1987
    Date of Patent: January 31, 1989
    Assignees: Hitachi Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Kohei Fukuoka, Satoshi Takemura, Yatao Takesue, Hisashi Tamaru