Patents by Inventor Yatender Mishra

Yatender Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8320201
    Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Kumar Gupta, Devesh Dwivedi, Sanjeev Kumar Jain, Yatender Mishra
  • Publication number: 20120188837
    Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).
    Type: Application
    Filed: March 30, 2012
    Publication date: July 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Amit Kumar GUPTA, Devesh DWIVEDI, Sanjeev Kumar JAIN, Yatender MISHRA
  • Publication number: 20100208538
    Abstract: A sensing circuit for a semiconductor memory includes a multiplexer coupled to a bit line and a data line coupling the multiplexer to a sense amplifier. The data line is configured to be precharged to a voltage level higher than a precharge voltage level of the bit line.
    Type: Application
    Filed: November 17, 2009
    Publication date: August 19, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Kumar Gupta, Devesh Dwivedi, Sanjeev Kumar Jain, Yatender Mishra
  • Publication number: 20100202221
    Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).
    Type: Application
    Filed: November 23, 2009
    Publication date: August 12, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Amit Kumar GUPTA, Devesh DWIVEDI, Sanjeev Kumar JAIN, Yatender MISHRA