Patents by Inventor Yatin Hoskote
Yatin Hoskote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100268931Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
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Patent number: 7774590Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.Type: GrantFiled: March 23, 2006Date of Patent: August 10, 2010Assignee: Intel CorporationInventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
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Patent number: 7668165Abstract: Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies.Type: GrantFiled: March 31, 2004Date of Patent: February 23, 2010Assignee: Intel CorporationInventors: Yatin Hoskote, Sriram R. Vangal, Vasantha K. Erraguntla, Nitin Y. Borkar
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Patent number: 7620119Abstract: A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.Type: GrantFiled: June 29, 2004Date of Patent: November 17, 2009Assignee: Intel CorporationInventors: Siva G. Narendra, Yatin Hoskote, Saurabh Dighe, Nitin Y. Borkar, Vivek K De
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Patent number: 7412353Abstract: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.Type: GrantFiled: September 28, 2005Date of Patent: August 12, 2008Assignee: Intel CorporationInventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
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Patent number: 7324540Abstract: The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).Type: GrantFiled: December 31, 2002Date of Patent: January 29, 2008Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Vasantha K. Erraguntla, Jianping Xu
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Publication number: 20070226482Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
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Publication number: 20070074011Abstract: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.Type: ApplicationFiled: September 28, 2005Publication date: March 29, 2007Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
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Patent number: 7181544Abstract: Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.Type: GrantFiled: September 3, 2002Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Patent number: 7024439Abstract: Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input operands using a leading zero anticipation (LZA) device. An algorithm is presented for leading zero and leading one anticipation that may be used to remove leading zeroes or ones from sums produced in arithmetic units. This algorithm and the design of the combinational logic does not require a comparison of input operands nor does it need two separate counters for leading zeros and leading ones as in most other LZAs. The present invention is especially applicable to redundant format addition.Type: GrantFiled: January 24, 2002Date of Patent: April 4, 2006Assignee: Intel CorporationInventor: Yatin Hoskote
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Patent number: 7016354Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.Type: GrantFiled: September 3, 2002Date of Patent: March 21, 2006Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Patent number: 6988119Abstract: The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.Type: GrantFiled: June 29, 2001Date of Patent: January 17, 2006Assignee: Intel CorporationInventors: Yatin Hoskote, Sriram R Vangai, Jason M Howard
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Publication number: 20050286655Abstract: A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Siva Narendra, Yatin Hoskote, Saurabh Dighe, Nitin Borkar, Vivek De
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Publication number: 20050226238Abstract: Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies.Type: ApplicationFiled: March 31, 2004Publication date: October 13, 2005Inventors: Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar
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Patent number: 6947962Abstract: An algorithm and implementation is described of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carry-save format in high speed arithmetic units.Type: GrantFiled: January 24, 2002Date of Patent: September 20, 2005Assignee: Intel CorporationInventor: Yatin Hoskote
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Publication number: 20050165985Abstract: Disclosed are techniques for processing a packet. A packet is received. Context data for the packet is located in a storage area. The packet is processed using the context data. Also disclosed is a network protocol processor with an interface to receive a packet, a cache to store context data for the packet, and a processing engine to process the packet using context data in the cache. Moreover, the network protocol processor includes a working register to store the context data for a current connection that is being processed. Additionally, the cache is capable of storing and retrieving context data for multiple connections.Type: ApplicationFiled: December 29, 2003Publication date: July 28, 2005Inventors: Sriram Vangal, Yatin Hoskote, Vasantha Erraguntla, Nitin Borkar
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Publication number: 20040193733Abstract: The disclosure describes packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.Type: ApplicationFiled: September 3, 2002Publication date: September 30, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Publication number: 20040125751Abstract: The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Vasantha K. Erraguntla, Jianping Xu
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Publication number: 20040044796Abstract: In general, in one aspect, the disclosure describes a method for use in tracking received out-of-order packets. Such a method can include receiving at least a portion of a packet that includes data identifying an order within a sequence, and based on the data identifying the order, requesting stored data identifying a set of contiguous previously received out-of-order packets having an ordering within the sequence that borders the received packet.Type: ApplicationFiled: September 3, 2002Publication date: March 4, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erranguntla, Shekhar Y. Borkar
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Publication number: 20040042497Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.Type: ApplicationFiled: September 3, 2002Publication date: March 4, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar