Patents by Inventor Yatin Mundkur
Yatin Mundkur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220305000Abstract: The present disclosure relates to the field of oncology and particularly towards a combination therapy for treatment of cancer. In particular, the present disclosure provides a combination therapy comprising chloroquine, metformin and statin, for treatment/management of Myeloproliferative neoplasms (MPNs) or any associated condition. The combinations of the present disclosure show a synergistic cytotoxic activity against cancer cells. The present disclosure also relates to a composition comprising said combination, and a method for treatment/management of MPN or any associated condition by employing said composition or combination therapy. The present disclosure also provides combination of chloroquine, metformin and statin for use in treatment/management of MPN or any associated condition.Type: ApplicationFiled: March 23, 2022Publication date: September 29, 2022Inventors: Ansu Kumar, Swati Khandelwal, Subrat Mohapatra, Himanshu Grover, Vivek Patil, Anuj Tyagi, Ashish Kumar Agrawal, Shweta Kapoor, Yatin Mundkur
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Patent number: 9525850Abstract: Display devices and systems including television sets, and systems, apparatus and methods for delivering information and providing services through display devices and systems. The display used in the described systems and methods is capable of receiving one or more TV programming channels and an independent designated application channel and having at least a first display window and a second display window separated from each other without spatial overlap on the screen. The information sent over the designated application channel to the display is displayed on the first display window while simultaneously displaying one of the TV programming channels on the second display window. A viewer control mechanism is provided in the display to allow the viewer to switch the information received from the designated application channel from the first display window to the second display window and switch back at the viewer's choice.Type: GrantFiled: March 20, 2008Date of Patent: December 20, 2016Assignee: PRYSM, INC.Inventors: Amit Jain, Yatin Mundkur, Roger A. Hajjar
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Patent number: 7548996Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: September 12, 2005Date of Patent: June 16, 2009Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, John Poole, legal representative, Ashok Raman, Eric Rehm, Radhika Thekkath, David Poole
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Patent number: 7457890Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: GrantFiled: October 30, 2006Date of Patent: November 25, 2008Assignee: Hitachi, Ltd.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20080235749Abstract: Display devices and systems including television sets, and systems, apparatus and methods for delivering information and providing services through display devices and systems. The display used in the described systems and methods is capable of receiving one or more TV programming channels and an independent designated application channel and having at least a first display window and a second display window separated from each other without spatial overlap on the screen. The information sent over the designated application channel to the display is displayed on the first display window while simultaneously displaying one of the TV programming channels on the second display window. A viewer control mechanism is provided in the display to allow the viewer to switch the information received from the designated application channel from the first display window to the second display window and switch back at the viewer's choice.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Applicant: Spudnik, Inc.Inventors: Amit Jain, Yatin Mundkur, Roger A. Hajjar
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Patent number: 7272670Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.Type: GrantFiled: February 5, 2001Date of Patent: September 18, 2007Assignee: HitachiInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7262720Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.Type: GrantFiled: June 30, 2003Date of Patent: August 28, 2007Assignee: Equator Technologies, Inc.Inventors: Richard M. Deeley, Yatin Mundkur, Woobin Lee
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Publication number: 20070130401Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: ApplicationFiled: October 30, 2006Publication date: June 7, 2007Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20060288134Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: ApplicationFiled: September 12, 2005Publication date: December 21, 2006Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath, John Poole
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Patent number: 7051123Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: November 10, 2000Date of Patent: May 23, 2006Assignees: Hitachi, Ltd., Equator Technologies, Inc.,Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, Ashok Raman, Eric Rehm, Radhika Thekkath
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Publication number: 20040255058Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: June 15, 2004Publication date: December 16, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040221071Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: February 5, 2001Publication date: November 4, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040081245Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.Type: ApplicationFiled: June 30, 2003Publication date: April 29, 2004Applicant: Equator Technologies, Inc.Inventors: Richard M. Deeley, Yatin Mundkur, Woobin Lee
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Publication number: 20030196040Abstract: An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.Type: ApplicationFiled: December 18, 2002Publication date: October 16, 2003Inventors: Koji Hosogi, Gregorio Gervasio, Yatin Mundkur, Radhika Thekkath
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Patent number: 6587058Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.Type: GrantFiled: October 25, 2002Date of Patent: July 1, 2003Assignee: Equator Technologies, Inc.Inventors: Richard M. Deeley, Yatin Mundkur, Woobin Lee
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Patent number: 6560674Abstract: An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.Type: GrantFiled: October 14, 1998Date of Patent: May 6, 2003Assignees: Hitachi, Ltd., Equater Technologies, Inc.Inventors: Koji Hosogi, Gregorio Gervasio, Yatin Mundkur, Radhika Thekkath
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Patent number: 6507293Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.Type: GrantFiled: December 21, 2000Date of Patent: January 14, 2003Assignee: Equator Technologies, Inc.Inventors: Richard M. Deeley, Yatin Mundkur, Woobin Lee
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Patent number: 6434649Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: October 14, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Equator TechnologiesInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath
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Patent number: 6347344Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.Type: GrantFiled: October 14, 1998Date of Patent: February 12, 2002Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20020011943Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.Type: ApplicationFiled: December 21, 2000Publication date: January 31, 2002Applicant: Equator Technologies, Inc.Inventors: Richard M. Deeley, Yatin Mundkur, Woobin Lee