Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

Abstract: Provided is a device with a replacement spacer structure and a method for forming such a structure. The method includes forming an initial spacer structure, wherein the initial spacer structure has an initial etch rate for a selected etchant. The method further includes removing a portion of the initial spacer structure, wherein a remaining portion of the initial spacer structure is not removed. Also, the method includes forming a replacement spacer structure adjacent to the remaining portion of the initial spacer structure to form a combined spacer structure, wherein the combined spacer structure has an intermediate etch rate for the selected etchant that is less than the initial etch rate for a selected etchant. Further, the method includes etching the combined spacer structure with the selected etchant to form a final spacer structure.

Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.

Abstract: A method for controlling bitstream decoding is provided. The bitstream includes a plurality of frames. The method includes: generating a performance indicator according to a decoding time of at least one previous frame; generating a dropping decision according to the performance indicator, wherein the dropping decision indicates whether it is needed to drop a frame; and determining whether to drop a current frame according to the dropping decision.

Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.

Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.

Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.

Abstract: An electrostatic discharge protection circuit and a display apparatus are provided. The electrostatic discharge protection circuit adapted to the display apparatus having a display panel which has a signal line and a common voltage line. The electrostatic discharge protection circuit includes a first switching unit and a second switching unit. The first switching unit is electrically coupled to the signal line. The second switching unit is electronically coupled between the first switching unit and the common voltage line. When the display apparatus is shut down, the first switching unit and the second switching unit form a conductive path. When the display apparatus is turned on, the first switching unit receives a first control signal, and the second switching unit receives a second control signal, so that at least one of the first switching unit and the second switching unit is turned off at the same time.

Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.

Abstract: An electrostatic discharge protection circuit and a display apparatus are provided. The electrostatic discharge protection circuit adapted to the display apparatus having a display panel which has a signal line and a common voltage line. The electrostatic discharge protection circuit includes a first switching unit and a second switching unit. The first switching unit is electrically coupled to the signal line. The second switching unit is electronically coupled between the first switching unit and the common voltage line. When the display apparatus is shut down, the first switching unit and the second switching unit form a conductive path. When the display apparatus is turned on, the first switching unit receives a first control signal, and the second switching unit receives a second control signal, so that at least one of the first switching unit and the second switching unit is turned off at the same time.

Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.

Abstract: A video codec method synchronizes long term reference frames in a video encoding device and a video decoding device of a video communication system. The video encoding device encodes video frames to code streams in an inter-prediction mode and set the corresponding reference frames to non-committed long term reference frames. The video decoding device decodes the code streams using the corresponding reference frames, then transmits an acknowledgement of the non-committed long term reference frames to the video encoding device. The video encoding device sets the non-committed long term reference frames to committed long term reference frames, and encodes succeeding video frames in the inter-prediction mode using the committed long term reference frames.

Abstract: A guard fence for use in a drop test includes a frame defining a test area, four support legs respectively connected to the frame for supporting the frame, and four buffer curtains made of elastic materials and respectively disposed between two adjacent support legs for encircling the test area. As a result, when a drop test is conducted, the buffer curtains can effectively prevent the test sample from an undesired impact.