Patents by Inventor Yatish Girish TURAKHIA

Yatish Girish TURAKHIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Architecture for sparse neural network acceleration
    Patent number: 10871964
    Abstract: A method, a computer-readable medium, and an apparatus for a sparse neural network are provided. The apparatus may include a hardware accelerator. The apparatus may determine, for each pair of operands to be processed by a MAR unit, whether both operands of the pair are non-zero. The apparatus may prevent a pair of operands to be processed by the MAR unit from being loaded to a multiplier of the MAR unit when an operand of the pair of operands is zero. The apparatus may place the pair of operands into one of a plurality of queues when both operands of the pair of operands are non-zero.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 22, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Yatish Girish Turakhia, Javid Jaffari, Amrit Panda, Karamvir Chatha
  • ARCHITECTURE FOR SPARSE NEURAL NETWORK ACCELERATION
    Publication number: 20180189056
    Abstract: A method, a computer-readable medium, and an apparatus for a sparse neural network are provided. The apparatus may include a hardware accelerator. The apparatus may determine, for each pair of operands to be processed by a MAR unit, whether both operands of the pair are non-zero. The apparatus may prevent a pair of operands to be processed by the MAR unit from being loaded to a multiplier of the MAR unit when an operand of the pair of operands is zero. The apparatus may place the pair of operands into one of a plurality of queues when both operands of the pair of operands are non-zero.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Yatish Girish TURAKHIA, Javid JAFFARI, Amrit PANDA, Karamvir CHATHA
  • LOW-POWER ARCHITECTURE FOR SPARSE NEURAL NETWORK
    Publication number: 20180164866
    Abstract: A method, a computer-readable medium, and an apparatus for reducing power consumption of a neural network are provided. The apparatus may retrieve, from a tag storage, at least one tag value of a first tag value for a weight in the neural network or a second tag value for an activation in the neural network. The first tag value may indicate whether the weight is zero and the second tag value may indicate whether the activation is zero. The weight and the activation are to be loaded to a multiplier of a multiplier-accumulator unit as a pair of operands. The apparatus may determine whether the at least one tag value indicates a zero value. The apparatus may disable loading the weight and the activation to the multiplier when the at least one tag value indicates a zero value. The apparatus may disable updating of zero-value activations.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: Yatish Girish TURAKHIA, Javid JAFFARI, Amrit PANDA, Karamvir CHATHA