Abstract: A process for fabricating non-volatile memory cells having improved voltage coupling ratio by utilizing liquid phase deposition. Polysilicon spacers resulting from the liquid phase deposition increase the surface area of the dielectric layer between floating gate and control gate layers.

Abstract: A new process for fabricating split-gate flash EEPROM memory cell on a semiconductor substrate is described. Source/drain regions are formed apart in the semiconductor substrate to define a channel there between. A tunnel oxide layer, a first conducting layer, and an dielectric layer are successfully formed overlying the semiconductor substrate. The dielectric layer, the first conducting layer, and the tunnel oxide layer are patterned by etching to expose portion of the channel and provide the first conducting layer forming a floating gate. Then, a first oxide layer is formed by thermal oxidation overlying the exposed surfaces of the floating gate and the channel. A second oxide layer is formed by deposition overlying the first oxide layer and the dielectric layer. A control gate layer is formed by depositing and etching a second conducting layer overlying the second oxide layer completing the split-gate flash EEPROM memory cell.