Abstract: An integrated circuit device is provided that has I/O bonding pads across the surface of the chip, where the I/O bonding pads can be electrically accessed via ancillary testing pads in order to perform functionality or other necessary tests prior to bump bonding formation without damaging the bonding pads or the underlying circuitry.

Abstract: This invention pertains to a lateral bipolar transistor comprising an emitter, a base and a collector. The transistor exhibits improved function and overall size reduction, due to the base and emitter structure. An island forms both the base and emitter regions in the transistor structure with the base region being above the collector region, below the emitter region, and surrounded by a dielectric region. The emitter is surrounded by emitter isolation walls, which are formed approximately 0.2 microns above the plane of the dielectric region, such that any manufacturing variances will not cause the emitter isolation walls to contact the dielectric region and pinch-off the base region from the base junction region. This structure also allows the size of the base-emitter junction to be decreased without increasing the parasitic characteristics of the transistor.

Abstract: A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.

Abstract: This invention pertains to a lateral bipolar transistor comprising an emitter, a base and a collector. The transistor exhibits improved function and overall size reduction, due to the base and emitter structure. An island forms both the base and emitter regions in the transistor structure with the base region being above the collector region, below the emitter region, and surrounded by a dielectric region. The emitter is surrounded by emitter isolation walls, which are formed approximately 0.2 microns above the plane of the dielectric region, such that any manufacturing variances will not cause the emitter isolation walls to contact the dielectric region and pinch-off the base region from the base junction region. This structure also allows the size of the base-emitter junction to be decreased without increasing the parasitic characteristics of the transistor.

Abstract: A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.