Abstract: Embodiments of the present invention relate to a system and method for detecting biological material on surfaces after decontamination with UV-C and with high sensitivity and having low detection limits while providing rapid and efficient response to accommodate high turnover. Embodiments of the present invention monitor the disinfection process by detecting changes in the electrical properties of surface-confined biological thin films photodegraded with UV-C radiation using microwaves (MW). MW sensing provides noninvasive, real-time detection of the electromagnetic properties of biological materials via concentrated electromagnetic fields, for which advantages include wide bandwidth, small size, and cost-effective fabrication.

Abstract: An electronic device comprising a substrate having a component-side surface and a moisture protection film covering the component-side surface. The moisture protection film includes a first water layer bonded to component-side surface that is an activated surface, wherein the activated surface has a lower water contact angle than the substrate surface before the surface activation. The film includes a first graphed layer of a plasma-reacted first set of precursor molecules graphed to the first water layer, wherein the first water layer forms a first bonding link between the substrate surface and the reacted first set precursor molecules. The film includes a second water layer bonded to the first graphed layer. The film includes a second graphed layer of a plasma-reacted second set of precursor molecules graphed to the second water layer, wherein the second water layer forms a second bonding link between the second water layer and the reacted second set of precursor molecules.

Abstract: A film deposition process comprising exposing a surface of a substrate to a first plasma treatment having plasma reactants in a plasma chamber to form an activated substrate surface. The activated surface has a lower water contact angle than the substrate surface before the surface activating. The process comprises introducing water vapor into the plasma chamber to form a water layer on the activated surface. The process comprises introducing pre-cursors molecules into the plasma chamber in the presence of a second plasma to graft a layer of reacted pre-cursor molecules on the water layer.

Abstract: A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

Abstract: A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

Abstract: A method of manufacturing a polymeric object that comprises providing a polymeric substrate, and exposing said substrate to a first stage that includes an initial plasma reactant so as to reduce a water contact angle of a surface of the substrate, and, wherein the initial plasma treatment activates the surface to a grafting reaction, The method further includes exposing the activated substrate surface to a second stage that includes a second plasma reactant to thereby deposit a grafted material on the activated substrate surface to form a grafted surface.

Abstract: In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.

Abstract: A ULSI circuit chip comprising copper interconnects is provided with a corrosion protection passivating layer on the surface of the copper which layer is comprised of a self assembled organic monolayer formed from treating the copper surface with a dilute solution of, for example a thio-bisalkyl acetoacetonate. A similar layer can be formed under the copper to provide a barrier layer against copper migration.

Abstract: A method for removing contaminants from integrated circuit devices. Particularly disclosed is a method for removing alkali metal and halogen-based contaminants from an integrated circuit device as the device is being fabricated.

Abstract: The specification describes a method and apparatus for chemical-mechanical polishing (CMP) to produce planar layered semiconductor structures. Non-uniformities in polishing behavior due to radial temperature variations across the semiconductor wafer are compensated by locally controlling the temperature of the wafer. Heating/cooling is implemented by installing temperature controlling coils in the head of the wafer carrier.

Abstract: A method of semiconductor circuit fabrication utilizing the poly buffered LOCOS process is disclosed. Amorphous silicon is desirably formed by the decomposition of disilane at temperatures between 400-525.degree. C. The amorphous silicon exhibits less pits than what is produced by conventional processes. The absence of pits contributes to eventual substrate integrity.

Abstract: A method of chemical mechanical polishing (CMP) useful in the manufacture of integrated circuits is disclosed. Waste slurry is examined and its conductivity, luminescence, or particulate mass evaluated to determine an endpoint for the CMP operation.

Abstract: A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.

Abstract: A method of chemical mechanical polishing (CMP) useful in the manufacture of integrated circuits is disclosed. Waste slurry is examined and its conductivity, luminescence, or particulate mass evaluated to determine an endpoint for the CMP operation.

Abstract: A method for CMP of, illustratively, tungsten is disclosed. Hydroxylamine or hydroxylamine sulfate are employed to oxidize the metal, while gamma (.gamma.) alumina is employed to abrade the oxidized metal.

Abstract: A process for forming a P.sub.2 O.sub.5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness.

Abstract: The quality of solvents used in semiconductor manufacturing for removing photoresist or post halogen etch cleanup is monitored by measuring the conductivity of the solvents.