Patents by Inventor Yawei Liang

Yawei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control
    Patent number: 11804470
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Kaizad Mistry, Paul R. Start, Nisha Ananthakrishnan, Yawei Liang, Jigneshkumar P. Patel, Sairam Agraharam, Liwei Wang
  • Integrated heat spreader comprising a silver and sintering silver layered structure
    Patent number: 11562940
    Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, James C. Matayabas, Jr., Yawei Liang, Yiqun Bai
  • WAFER LEVEL PASSIVE HEAT SPREADER INTERPOSER TO ENABLE IMPROVED THERMAL SOLUTION FOR STACKED DIES IN MULTI-CHIPS PACKAGE AND WARPAGE CONTROL
    Publication number: 20210057381
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Xavier F. BRUN, Kaizad MISTRY, Paul R. START, Nisha ANANTHAKRISHNAN, Yawei LIANG, Jigneshkumar P. PATEL, Sairam AGRAHARAM, Liwei WANG
  • INTEGRATED HEAT SPREADER COMPRISING A SILVER AND SINTERING SILVER LAYERED STRUCTURE
    Publication number: 20200286806
    Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Elizabeth Nofen, James C. Matayabas, JR., Yawei Liang, Yiqun Bai