Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.

Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Abstract: Systems and methods for improving decoding of encoded image data using parallel multi-bin decoding are provided. In one embodiment, multiple context bins per cycle are decoded for a set of syntax elements, by decoupling and/or retiming particular syntax parsing and/or arithmetic decoding tasks of the decoding process.

Abstract: A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M?1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

Abstract: Systems and methods for improving decoding of encoded image data using parallel multi-bin decoding are provided. In one embodiment, multiple context bins per cycle are decoded for a set of syntax elements, by decoupling and/or retiming particular syntax parsing and/or arithmetic decoding tasks of the decoding process.

Abstract: A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M?1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter.

Abstract: A latch and a D flip-flop, where the latch includes a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. The voltage converter is configured to output an output signal of the latch according to an input signal of the latch when the switch is in an on state, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. A circuit structure of the latch is simple and integrity of an existing logic circuit can be improved.

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter.

Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

Abstract: An architecture capable of carrying out variable length decoding for multiple video compression formats (e.g., MPEG1/2/4, H.263, H.264, Microsoft WMV9, and Sony Digital Video), is disclosed. In one embodiment, the VLD process is divided into two parts: flow control and table lookup. The flow control part can be performed by a low-cost microcontroller or other suitable processor, and the table lookup part is performed by hardware logic. With different firmware, the microcontroller handles flow control of all the existing video formats and can be adapted to accommodate new formats without any hardware change. Each piece of lookup table logic is connected to the microcontroller as extended instructions. In operation, during the decoding process, the flow control firmware executes one of these extended instructions whenever a table lookup operation is required. The architecture can be implemented, for example, as a system-on-chip decoder for use in HDTV applications and the like.

Abstract: Video coders use motion prediction, where a reference frame is used to predict a current frame. Most video compression standards require reference frame buffering and accessing. Given the randomized memory accesses to store and access reference frames, there are substantial overlapped areas. Conventional techniques fail to recognize this overlap, and perform duplicate loading, thereby causing increased memory traffic. Techniques disclosed herein reduce the memory traffic by avoiding the duplicated loading of overlapped area, by using a reference cache that is interrogated for necessary reference data prior to accessing reference memory. If the reference data is not in the cache, then that data is loaded from the memory and saved into the cache. If the reference data is in the cache, then that data is used instead of loading it from memory again. Thus, memory traffic is reduced by avoiding duplicated memory access to overlapped areas.

Abstract: A motion detection system can detect motion at a macroblock level of granularity and take an action based on the detection of motion or an event in a specified region of interest. The system comprises an ASIC capable of detecting an event in a macroblock of a frame of a video sequence, and an eventing engine for, responsive to the detection of the event by the ASIC, performing an action. Such a system can be configured by a user who provides an input specifying a region of interest on which motion detection should be performed by the motion detection system and a threshold value for determining whether or not motion has occurred in the region of interest.