Abstract: Provided is a method for correcting a lithography pattern of a surface plasma, including: forming a plurality of test patterns on a test mask; exposing a photoresist layer by using the test mask containing the test patterns to form a plurality of photoresist patterns; establishing a first data table based on a correspondence between the first test parameter and the second test parameter of the test pattern and the first exposure parameter and the second exposure parameter of the photoresist pattern; processing the first data table according to the first exposure parameter to obtain a second data table; and respectively correcting second test parameters of a plurality of design patterns according to the second data table to obtain corrected design patterns, and manufacturing a mask for exposure by using the corrected design patterns.

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

Abstract: Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: A process is provided for the removal of defects, for example, micro-bridging defects during device fabrication. In one aspect, a method includes: obtaining a wafer after lithography processing and exposing the wafer to at least one electron beam. In another aspect, a system includes: selecting a substrate with micro-bridging defects after the substrate undergoes lithography processing; preparing the substrate for exposure to at least one electron beam; and exposing the substrate to the at least one electron beam.

Abstract: A process is provided for the removal of defects, for example, micro-bridging defects during device fabrication. In one aspect, a method includes: obtaining a wafer after lithography processing and exposing the wafer to at least one electron beam. In another aspect, a system includes: selecting a substrate with micro-bridging defects after the substrate undergoes lithography processing; preparing the substrate for exposure to at least one electron beam; and exposing the substrate to the at least one electron beam.

Abstract: An approach for enhancing resolution in a lithographic process (e.g., an immersion lithographic process) is provided. Specifically, a material having a high reflexive index (e.g., water) is provided on opposite sides of an objective lens. This allows a set of light rays (high intensity) to be directed/passed from a light source, through a condenser lens, over a mask, through the material positioned on one side of the objective lens, through the objective lens, through the material on the opposite side of the objective lens, and to a wafer that is then patterned. Positioning the material on both sides of the objective lens allows for improved resolution and lithographic patterning of the wafer for both on-axis illumination and off-axis illumination techniques.

Abstract: One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: Embodiments of the invention provide a method for spin coating a film onto a substrate. Preferred embodiments deposit a film, such as a resist, having a thickness gradient from the substrate's centrifugal center to its edge. The gradient may be linear or stepwise continuous, for example. Other embodiments of the invention provide a semiconductor fabrication method. The method comprises forming a resist layer having a predetermined thickness on a substrate. Preferably, the predetermining includes making swing curve measurements on a single test wafer that is coated according to embodiments of the invention.

Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

Abstract: Masks for patterning material layers of semiconductor devices, methods of manufacturing semiconductor devices, and lithography systems are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a lithography mask, the lithography mask including at least one attenuation region. The at least one attenuation region includes an array of sub-resolution features. A workpiece is provided, the workpiece having a layer of photosensitive material disposed thereon. The layer of photosensitive material is affected using the lithography mask.