Abstract: A host vehicle information acquiring unit acquires host vehicle information indicating both a signal of a course change that a vehicle is to make, and a traveling direction in which the vehicle is to head because of the course change. An approaching object information acquiring unit acquires approaching object information indicating one or more approaching objects approaching the vehicle in a predetermined region in surroundings of the vehicle. An effective field of view determining unit determines an effective field of view of the driver of the vehicle. A target specifying unit specifies, out of the approaching objects approaching the vehicle, an approaching object approaching from a side opposite to the traveling direction in which the vehicle is to head on the basis of the host vehicle information and the approaching object information, and sets the specified approaching object as a target.

Abstract: A position of a virtual image corresponding to a display image in a view outside a vehicle is adjusted by adjustment of the display image. An adjustment device includes an adjustment unit for performing adjustment of the display image depending on operation input to an operation input device in a state where reference light, serving as a reference for the position of the virtual image, is emitted to a road surface, and an adjustment condition determining unit for detecting an adjustable distance range, in which the adjustment can be performed, in an adjustment target distance range set to be subjected to the adjustment, in which the adjustment unit performs the adjustment of the display image corresponding to the virtual image in the adjustable distance range in a state where the reference light is emitted to a road surface in the adjustable distance range.

Abstract: A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.

Abstract: A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.