Patents by Inventor Yazdan Aghaghiri

Yazdan Aghaghiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Consistent hierarchical timing model with crosstalk consideration
    Patent number: 8468479
    Abstract: A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: June 18, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peivand Tehrani, Li Ding, Narender Hanchate, Rupesh Nayak, Yazdan Aghaghiri
  • Consistent Hierarchical Timing Model with Crosstalk Consideration
    Publication number: 20120239371
    Abstract: A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Inventors: Peivand Tehrani, Li Ding, Narender Hanchate, Rupesh Nayak, Yazdan Aghaghiri
  • System and method for identifying optimal encoding for a given trace
    Patent number: 7236107
    Abstract: A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: June 26, 2007
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • System and method for identifying optimal encoding for a given trace
    Publication number: 20060061492
    Abstract: A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.
    Type: Application
    Filed: September 20, 2004
    Publication date: March 23, 2006
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • Reducing transitions on address buses using instruction-set-aware system and method
    Patent number: 6907511
    Abstract: An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: June 14, 2005
    Assignees: Fujitsu Limited, University of Southern California
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • System and method for reducing transitions on address buses
    Patent number: 6834335
    Abstract: An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: December 21, 2004
    Assignees: Fujitsu Limited, University of Southern California
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • Reduction of bus switching activity using an encoder and decoder
    Patent number: 6813700
    Abstract: An encoder and decoder provide coding of information communicated on busses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: November 2, 2004
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • Reducing transitions on address buses using instruction-set-aware system and method
    Publication number: 20030101326
    Abstract: An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.
    Type: Application
    Filed: January 14, 2003
    Publication date: May 29, 2003
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • System and method for reducing transitions on address buses
    Publication number: 20030051120
    Abstract: An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
    Type: Application
    Filed: August 9, 2002
    Publication date: March 13, 2003
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram
  • Reduction of bus switching activity
    Publication number: 20020194453
    Abstract: An encoder and decoder provide coding of information communicated on busses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
    Type: Application
    Filed: June 3, 2002
    Publication date: December 19, 2002
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Yazdan Aghaghiri, Massoud Pedram