Patents by Inventor Yazhou Zhang
Yazhou Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12230953Abstract: In aspects of the present disclosure, a circuit interrupter includes a housing, a conductive path, a switch which selectively interrupts the conductive path, sensor(s), memory, and a controller within the housing. The sensor(s) measure electrical characteristic(s) of the conductive path. The memory stores an arc detection program that implements a machine learning model and includes a field-updatable program portion and a non-field-updatable program portion, where the field-updatable program portion includes program parameters used by the non-field-updatable program portion to decide between presence or absence of an arc fault. The controller executes the arc detection program to compute input data for the machine learning model based on the sensor measurements, decide between presence of an arc event or absence of an arc event based on the input data, and cause the switch to interrupt the conductive path when the decision indicates presence of an arc event.Type: GrantFiled: May 18, 2022Date of Patent: February 18, 2025Assignee: Leviton Manufacturing Co., Inc.Inventors: Yazhou Zhang, Michael Ostrovsky, Ankit Sanghvi, Adam Kevelos
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Patent number: 11901260Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.Type: GrantFiled: September 2, 2022Date of Patent: February 13, 2024Assignee: Western Digital Technologies, Inc.Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
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Patent number: 11837476Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.Type: GrantFiled: May 15, 2020Date of Patent: December 5, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
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Publication number: 20230053431Abstract: In aspects of the present disclosure, a circuit interrupter includes a housing, a conductive path, a switch which selectively interrupts the conductive path, sensor(s), memory, and a controller within the housing. The sensor(s) measure electrical characteristic(s) of the conductive path. The memory stores an arc detection program that implements a machine learning model and includes a field-updatable program portion and a non-field-updatable program portion, where the field-updatable program portion includes program parameters used by the non-field-updatable program portion to decide between presence or absence of an arc fault. The controller executes the arc detection program to compute input data for the machine learning model based on the sensor measurements, decide between presence of an arc event or absence of an arc event based on the input data, and cause the switch to interrupt the conductive path when the decision indicates presence of an arc event.Type: ApplicationFiled: May 18, 2022Publication date: February 23, 2023Inventors: Yazhou Zhang, Michael Ostrovsky, Ankit Sanghvi, Adam Kevelos
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Publication number: 20230011439Abstract: A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.Type: ApplicationFiled: July 7, 2021Publication date: January 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu
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Publication number: 20220415750Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
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Patent number: 11508644Abstract: A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.Type: GrantFiled: February 26, 2021Date of Patent: November 22, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Shineng Ma, Kent Yang, Hope Chiu
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Patent number: 11488883Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.Type: GrantFiled: April 13, 2021Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
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Publication number: 20220328374Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.Type: ApplicationFiled: April 13, 2021Publication date: October 13, 2022Applicant: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
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Patent number: 11444001Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.Type: GrantFiled: May 7, 2021Date of Patent: September 13, 2022Assignee: Western Digital Technologies, Inc.Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
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Publication number: 20220216128Abstract: A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.Type: ApplicationFiled: February 26, 2021Publication date: July 7, 2022Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Shineng Ma, Kent Yang, Hope Chiu
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Patent number: 11355485Abstract: A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.Type: GrantFiled: March 13, 2020Date of Patent: June 7, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Chin-Tien Chiu, Shineng Ma
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Patent number: 11348254Abstract: A visual search method, a computer device, and a non-transitory computer readable storage medium are provided. An ith image frame is received. The location and the classification of the subject in the ith image frame are extracted. A detection block corresponding to the subject is generated. In subsequent image frames of the ith image frame, the subject is tracked on the basis of the location of the subject in the ith image frame. The detection block is adjusted on the basis of the tracking result.Type: GrantFiled: July 1, 2019Date of Patent: May 31, 2022Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.Inventors: Liuqing Zhang, Guohong Li, Xin Qiu, Shuhui Gao, Yazhou Zhang
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Publication number: 20220154046Abstract: The present invention relates to an electrically conductive composition comprising a silicone resin comprising at least one vinyl-group; a silicone cross-linker having at least one Si—H group; electrically conductive particles; a solvent; an adhesion promoter; a catalyst; and an inhibitor, wherein ratio between Si—H groups and vinyl-groups is equal or greater than 1.3 but equal or less than 10.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Anja Henckens, Elisabeth Theunissen, Jing Yang, Yazhou Zhang, Yifan Chen
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Patent number: 11257785Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.Type: GrantFiled: March 13, 2020Date of Patent: February 22, 2022Assignee: Western Digital Technologies, Inc.Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang
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Patent number: 11177239Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.Type: GrantFiled: March 8, 2018Date of Patent: November 16, 2021Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.Inventors: Shineng Ma, Chin-Tien Chiu, Chih-Chin Liao, Ye Bai, Yazhou Zhang, Yanwen Bai, Yangming Liu
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Publication number: 20210335628Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.Type: ApplicationFiled: May 15, 2020Publication date: October 28, 2021Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
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Patent number: 11128115Abstract: The present disclosure relates to arc fault detection in an electrical switch apparatus. In aspects of the present disclosure, an arc fault electrical switch apparatus includes a conductive path, a switch configured to interrupt electrical current in the conductive path, a current sensor in electrical communication with the conductive path and configured to measure the electrical current to provide current measurements, and a controller. The controller is configured to execute instructions to sample the current measurements to provide current samples, computing an estimated signal-to-noise ratio of the electrical current based on at least a portion of the current samples, determine whether the signal-to-noise ratio is less than a predetermined threshold, and activate the switch to interrupt the electrical current in the conductive path, if the signal-to-noise ratio is less than the predetermined threshold.Type: GrantFiled: August 21, 2019Date of Patent: September 21, 2021Assignee: Leviton Manufacturing Co., Inc.Inventors: Steven Kay, Yazhou Zhang, Alan Neal, Ankit Sanghvi, Michael Ostrovsky
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Patent number: 11031378Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.Type: GrantFiled: March 13, 2020Date of Patent: June 8, 2021Assignee: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
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Publication number: 20210057900Abstract: The present disclosure relates to arc fault detection in an electrical switch apparatus. In aspects of the present disclosure, an arc fault electrical switch apparatus includes a conductive path, a switch configured to interrupt electrical current in the conductive path, a current sensor in electrical communication with the conductive path and configured to measure the electrical current to provide current measurements, and a controller. The controller is configured to execute instructions to sample the current measurements to provide current samples, computing an estimated signal-to-noise ratio of the electrical current based on at least a portion of the current samples, determine whether the signal-to-noise ratio is less than a predetermined threshold, and activate the switch to interrupt the electrical current in the conductive path, if the signal-to-noise ratio is less than the predetermined threshold.Type: ApplicationFiled: August 21, 2019Publication date: February 25, 2021Inventors: Steven Kay, Yazhou Zhang, Alan Neal, Ankit Sanghvi, Michael Ostrovsky