Patents by Inventor Yejin Jeong

Yejin Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230311368
    Abstract: Disclosed is a conformal cooling channel design method using a topology optimization design. The conformal cooling channel design method using a topology optimization design according to an embodiment of the present invention includes the steps of: classifying a molded product as a thin structure or a bulk structure, and determining a cooling target area; decomposing the cooling target area into cooling target surfaces of two-dimensional shape; forming cooling channels independent from each other using a topology optimization design for each of the cooling target surfaces; and forming a conformal cooling channel by combining the cooling channels. According to the present embodiment, there is provided a method of designing a conformal cooling channel inside a mold after determining a cooling target surface by classifying the shape of a molded product as a bulk structure or a thin structure and forming an independent cooling channel for each cooling target surface using a topology optimization design.
    Type: Application
    Filed: March 14, 2022
    Publication date: October 5, 2023
    Inventors: Sungwoo BAE, Heonjae CHOO, Hyojae JANG, Yongsuk BARK, Yejin JEONG, Seunghyun YU
  • Publication number: 20230315050
    Abstract: Disclosed is a conformal cooling channel design method using deep learning and a topology optimization design. The conformal cooling channel design method using deep learning and a topology optimization design according to an embodiment of the present invention includes the steps of: classifying a molded product as a thin structure or a bulk structure, and determining a cooling target area; decomposing the cooling target area into cooling target surfaces of two-dimensional shape; producing a preprocessed image by performing a preprocessing step on an image of the cooling target surface to which a thermal load is reflected; forming cooling channels independent from each other, to which a topology optimization design is applied, for each of the cooling target surfaces by inputting the preprocessed image into a previously trained neural network; and forming a conformal cooling channel by combining the cooling channels.
    Type: Application
    Filed: March 14, 2022
    Publication date: October 5, 2023
    Inventors: Sungwoo BAE, Heonjae CHOO, Hyojae JANG, Yongsuk BARK, Yejin JEONG, Seunghyun YU
  • Patent number: 11733603
    Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 22, 2023
    Inventors: Taehoon Kim, Jaeho Jeong, Jeonghoon Ko, Jongwon Kim, Yejin Jeong, Changwook Jeong
  • Publication number: 20210405521
    Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.
    Type: Application
    Filed: February 22, 2021
    Publication date: December 30, 2021
    Inventors: Taehoon Kim, Jaeho Jeong, Jeonghoon Ko, Jongwon Kim, Yejin Jeong, Changwook Jeong