Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

Abstract: An electronic package is provided. The electronic package comprises a substrate having a first region and a second region; a first set of electronic components mounted on the substrate in the first region; a second set of electronic components mounted on the substrate in the second region; an encapsulant layer disposed on the substrate and encapsulating the first and second sets of electronic components; a set of interconnect components disposed on the substrate in the second region, and extending through the encapsulant layer, wherein the set of interconnect components are electrically coupled to the first and second sets of electronic components; and a connector mounted on the encapsulant layer and electrically coupled to the first and second sets of electronic components through the set of interconnect components.

Abstract: A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.

Abstract: A semiconductor device includes a lower circuit pattern on a substrate, a common source plate (CSP) on the lower circuit pattern, a gate electrode structure including gate electrodes spaced apart from each other on the CSP in a first direction that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction that is substantially parallel to the upper surface of the substrate, a first insulation pattern structure on a portion of the CSP that is adjacent to the gate electrode structure in the second direction, and a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure that is adjacent to the first insulation pattern structure.

Abstract: Provided is a method for forming a partial shielding for an electronic assembly, comprising: providing an electronic assembly mounted on a mother board, wherein the electronic assembly comprises a substrate, and at least one electronic component and a conductive pattern mounted on a top surface of the substrate; disposing a mask onto the substrate to cover the at least one electronic component; forming an encapsulant layer on the mother board to encapsulate at least the electronic assembly; forming a trench through the encapsulant layer to expose at least a portion of the conductive pattern and at least a portion of lateral surfaces of the mask; forming a shielding layer on the mother board to cover the encapsulant layer and fill in the trench; and detaching the mask from the mother board.

Abstract: An electronic package comprises: a substrate comprising a first region and a second region adjacent to the first region in a lengthwise direction of the substrate; a first electronic component mounted on the substrate in the first region; a second electronic component mounted on the substrate in the second region, wherein the second electronic component does not occupy an entirety of the substrate in a widthwise direction of the substrate; and an encapsulant layer formed on the substrate, wherein at least the second electronic component is exposed from the encapsulant layer, and wherein the encapsulant layer extends from the first region to the second region to reinforce the substrate in both the first region and the second region.

Abstract: A semiconductor device includes a substrate; a conductive layer; and a contact plug connected to the conductive layer. The contact plug includes a first portion; and a second portion, sequentially stacked, wherein a width of an upper surface of the first portion is wider than a width of a lower surface of the second portion. The contact plug includes a barrier layer; a first conductive layer on the barrier layer; and a second conductive layer on the first conductive layer. The second conductive layer comprises voids. The barrier layer, the first conductive layer, and the second conductive layer extend continuously in the first and second portions. The barrier layer has a first thickness, the second conductive layer has a second thickness, equal to or greater than the first thickness, and the first conductive layer has a third thickness, equal to or greater than the second thickness.

Abstract: The present invention relates to a method of manufacturing a cell spheroid using three-dimensional bio-printing technology, and the cell spheroid may be used for preventing or treating vascular and endocrine diseases by including mesenchymal stem cells, induced pluripotent stem cells-derived cells, or the like as an active ingredient, or may be used as an in vitro drug testing model.