Abstract: An image encoding/decoding method, device and recording medium based sed on multiple compression levels disclosure may include extracting a region of interest for machine vision from an input image, determining a compression level of the region of interest, and encoding the compression level of the region of interest.

Abstract: An object-based image encoding/decoding method and device of the present disclosure may include an image partition step which partitions an image to obtain a first object region, a region scaling step which scales the first object region based on a scaling factor of the first object region to obtain a second objection region, a region merging step which merges the second object region with at least one of an object region different from the second object region or a non-object region to obtain a merged image, and an image reconstruction step which reconstructs the merged image.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes: specific resistivities a first conductive line disposed on a substrate and extending in a first direction; a second conductive line disposed above the first metal wiring; a plurality of variable resistance structures each of which includes a plurality of electrodes and a plurality of variable resistance patterns alternately stacked between the first metal wiring and the second metal wiring, wherein the plurality of variable resistance patterns are formed of a variable resistance material having a same composition, and the plurality of electrodes have different material characteristics such as different specific resistivities.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes: specific resistivities a first conductive line disposed on a substrate and extending in a first direction; a second conductive line disposed above the first metal wiring; a plurality of variable resistance structures each of which includes a plurality of electrodes and a plurality of variable resistance patterns alternately stacked between the first metal wiring and the second metal wiring, wherein the plurality of variable resistance patterns are formed of a variable resistance material having a same composition, and the plurality of electrodes have different material characteristics such as different specific resistivities.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.

Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.

Abstract: A method an apparatus for drying a wafer, and an apparatus for cleaning and drying a wafer are provided. In the apparatus for cleaning and drying a wafer, the wafer is dipped into a cleaning solution in a cleaning tank. The wafer is then dried using a drying gas in a drying chamber disposed over the cleaning tank. A shutter separates the cleaning tank from the drying tank. A wafer boat moves the wafer vertically between the cleaning tank and the drying tank. Nozzles for providing the cleaning solution onto the wafer are disposed at both inner sides of the drying tank. The nozzles are connected to a drying gas supply unit to alternately and periodically provide the drying gas onto the wafer.

Abstract: A method an apparatus for drying a wafer, and an apparatus for cleaning and drying a wafer are provided. In the apparatus for cleaning and drying a wafer, the wafer is dipped into a cleaning solution in a cleaning tank. The wafer is then dried using a drying gas in a drying chamber disposed over the cleaning tank. A shutter separates the cleaning tank from the drying tank. A wafer boat moves the wafer vertically between the cleaning tank and the drying tank. Nozzles for providing the cleaning solution onto the wafer are disposed at both inner sides of the drying tank. The nozzles are connected to a drying gas supply unit to alternately and periodically provide the drying gas onto the wafer.