Patents by Inventor Ye Shao

Ye Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240130448
    Abstract: A reusable protective clothing includes a one-piece protective suit which includes integrated top and trousers attached with gloves and shoe covers, and a protective headpiece having a face shield. A front side of the protective headpiece is provided with a full-vision goggle with 180-degree field of view, the full-vision goggle is integrated with the face shield, a back side of the protective headpiece is provided with a protective hood made of a material of the one-piece protective suit, the protective hood is integrated with the top, the front side of the protective headpiece is provided with an air vent for a mouth and a nose configured according to facial features of a wearer, and an outer side of the protective headpiece is provided with ear-shaped hooks. The protective clothing is designed according to application environment and medical requirements to prevent exposure to pathogenic microorganisms.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 25, 2024
    Inventors: LEI ZHANG, YUZHANG SHAO, DEAN ZHAO, YE LI, LEJI WEN, XIN LIN
  • Patent number: 11626317
    Abstract: A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.
    Type: Grant
    Filed: October 24, 2020
    Date of Patent: April 11, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Patent number: 11587864
    Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Poornika Fernandes, Ye Shao, Guruvayurappan S. Mathur, John K. Arch, Paul Stulik
  • Publication number: 20220348913
    Abstract: The present disclosure discloses a method for identifying a M1 generation plant mutant resulting from physical and chemical mutagenesis, a method for acquiring the plant mutant, a mutant gene, and use thereof. The method for identifying a M1 generation plant mutant resulting from physical and chemical mutagenesis includes: mutagenizing a plant to obtain an M1 generation plant mutant, extracting a mixed pool of DNA from the obtained M1 generation plant mutant, subjecting the mixed pool of DNA to high-depth targeted sequencing for a target gene region, and aligning a sequencing result with the target gene region to identify whether there are target single nucleotide polymorphisms (SNPs) and/or Indel. The method of the present disclosure has high efficiency and high accuracy, involves simple operations, and is of progressive significance for the identification and acquisition of innovative germplasms.
    Type: Application
    Filed: June 2, 2022
    Publication date: November 3, 2022
    Inventors: Bingran Zhao, Ye Shao, Bigang Mao, Li Tang, Yan Peng, Yuanyi Hu, Wenjian Li, Lixia Yu, Yan Du, Yaokui Li, Dan Zhang, Lianyang Bai, Longping Yuan
  • Publication number: 20220130717
    Abstract: A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.
    Type: Application
    Filed: October 24, 2020
    Publication date: April 28, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Publication number: 20220093507
    Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Poornika FERNANDES, Ye SHAO, Guruvayurappan S. MATHUR, John K. ARCH, Paul STULIK
  • Patent number: 11222841
    Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Poornika Fernandes, Ye Shao, Guruvayurappan S. Mathur, John K. Arch, Paul Stulik
  • Publication number: 20210351269
    Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Patent number: 11101342
    Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Publication number: 20210249505
    Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Publication number: 20210074629
    Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Poornika FERNANDES, Ye SHAO, Guruvayurappan S. MATHUR, John K. ARCH, Paul STULIK
  • Patent number: 10840322
    Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dhishan Kande, Ye Shao, David Curran
  • Publication number: 20190305074
    Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Dhishan Kande, Ye Shao, David Curran
  • Publication number: 20190106881
    Abstract: A light gauge steel joist basic structure system of a light partition wall is disclosed, comprising: top and ground joists and vertical joists. The top and ground joists comprise a ground joist and a top joist. The vertical joist is provided between the top and ground joists by means of a first connection member. The vertical joist and the vertical joist are fixedly connected to each other by means of the first connection member and/or a second connection member. V-shaped slots are symmetrically provided on two side walls of the top and ground joists. The V-shaped slots are provided on the side walls and the bottoms of the vertical joists. A construction method for a light gauge steel joist basic structure of a light partition wall is also disclosed. The light gauge steel joist basic structure system is simple and fast to be constructed and has desirable flatness.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 11, 2019
    Applicants: DONCCUAN VANKE BUILDING TECHNIQUE RESEARCH CO., LTD., BEIJING JUMPSUN NEW TECHNOLOGY CO., LTD.
    Inventors: Yu Shi, Cheng Huang, Jiangping Sun, Ye Shao, Shuangxi Tian