Patents by Inventor Ye-sin Ryu

Ye-sin Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10156995
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Ye-Sin Ryu, Seong-Jin Cho
  • Patent number: 10127102
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye-Sin Ryu, Hoi-Ju Chung, Sang-Uhn Cha, Young-Yong Byun, Seong-Jin Jang
  • Publication number: 20180159558
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Application
    Filed: October 20, 2017
    Publication date: June 7, 2018
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu, Young-Sik Kim, Su-Yeon Doo
  • Publication number: 20180150350
    Abstract: A scrubbing controller of a semiconductor memory device includes a scrubbing address generator and a weak codeword address generator. The scrubbing address generator generates a scrubbing address for all codewords in a first bank array of a plurality of bank arrays in a first scrubbing mode. The scrubbing address is associated with a normal scrubbing operation and changes in response to an internal scrubbing signal and a scrubbing command. The weak codeword address generator generates a weak codeword address for weak codewords in the first bank array in a second scrubbing mode. The weak codeword address is associated with a weak scrubbing operation and is generated in response to the internal scrubbing signal.
    Type: Application
    Filed: September 1, 2017
    Publication date: May 31, 2018
    Inventors: SANG-UHN CHA, YE-SIN RYU
  • Publication number: 20180152206
    Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.
    Type: Application
    Filed: July 31, 2017
    Publication date: May 31, 2018
    Inventors: Hoon SIN, Sang-Uhn CHA, Ye-Sin RYU, Seong-Jin CHO
  • Patent number: 9953725
    Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-Sin Ryu, Sang-Uhn Cha, Hoi-Ju Chung, Seong-Jin Cho
  • Publication number: 20180060194
    Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.
    Type: Application
    Filed: May 16, 2017
    Publication date: March 1, 2018
    Inventors: Ye-Sin RYU, Jong-Wook PARK, Youn-Hyung KANG
  • Publication number: 20170308299
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.
    Type: Application
    Filed: January 4, 2017
    Publication date: October 26, 2017
    Inventors: SANG-UHN CHA, HOI-JU CHUNG, YE-SIN RYU, SEONG-JIN CHO
  • Publication number: 20170110206
    Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Ye-Sin Ryu, Sang-Uhn Cha, Hoi-Ju Chung, Seong-Jin Cho
  • Publication number: 20170083401
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.
    Type: Application
    Filed: August 5, 2016
    Publication date: March 23, 2017
    Inventors: Ye-sin Ryu, Hoi-Ju CHUNG, Sang-Uhn CHA, Young-Yong BYUN, Seong-Jin JANG