Abstract: A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit.

Abstract: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module (320) such that data arrives at the inputs of the mathematical operation module (320) substantially simultaneously. A first data hold module (604) communicates a first data valid signal to a second data hold module (606) upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data.

Abstract: A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit.

Abstract: Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Abstract: An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.

Abstract: A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

Abstract: One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for data processing (300), each programmable element (300) including a host interface (305) for receiving host data and a host control signal from the host, a crosspoint switch (318), and an interpolation module (310). The host data includes a serial stream of input data values. The interpolation module (310) selectively inserts one or more interpolation data values, such as zero, between selected ones of the input data values according to the host control signal, and communicates the input data values and interpolation data values to the crosspoint switch (318).

Abstract: Methods and systems for modeling concurrent behavior in a sequential programming environment using sequential-execution languages to describe and model multiple different processes which are running simultaneously.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for data processing (300), each programmable element (300) including a host interface (305) for receiving host data and a host control signal from the host, a crosspoint switch (318), and an interpolation module (310). The host data includes a serial stream of input data values. The interpolation module (310) selectively inserts one or more interpolation data values, such as zero, between selected ones of the input data values according to the host control signal, and communicates the input data values and interpolation data values to the crosspoint switch (318).

Abstract: A programmable accumulation module (324) with an embedded register array comprises a crosspoint switch (318), a control interface for receiving a control signal (359), a register array circuit (352), a multiplier module (348) for receiving two input values from the crosspoint switch (318) and multiplying the values, and an adder module (350) for adding an output of the multiplier module (348) with an output of the register array circuit (352). The register array circuit includes a plurality of data registers (356), an input multiplexer (354) for receiving an add result from the adder module and communicating the add result to one of the plurality of data registers (356) according to the control signal, and an output multiplexer (358) for receiving an output value from each of the plurality of data registers (356) and selectively communicating one of the plurality of output values to the adder module (350) according to the control signal.

Abstract: A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

Abstract: An integrated circuit (102) in communication with a host circuit (104) includes an interconnect bus (344) and a plurality of programmable elements (116-130). Each of the programmable elements (116-130) includes a control interface (354) for receiving a control signal, the control signal causing the memory element (338) to selectively operate in one of a plurality of modes. In a first mode, the memory element (338) communicates stored data to the output port upon receiving the control signal; in a second mode the memory element (338) communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element (338) stores a second data value consisting of at least a portion of each of two separate input values received at the input port.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module (320) such that data arrives at the inputs of the mathematical operation module (320) substantially simultaneously. A first data hold module (604) communicates a first data valid signal to a second data hold module (606) upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: Systems and methods are disclosed for mapping large multiplexers defined in VHDL (Very high speed integrated circuit Hardware Description Language) code to circuitry within an FPGA (field programmable gate array) in order to reduce the time required to synthesize and decompose such VHDL structures into FPGAs. It was recognized that large multiplexers within a VHDL device description can cause significant delays in the synthesis and decomposition processes for forming FPGAs based upon the VHDL code. By splitting the multiplexer into a multiple level cascaded multiplexer structure, a significant reduction can be achieved in the time it takes to accomplish the synthesis and decomposition process for FPGAs. The determination of whether the multiplexer is large and should be split can be made by a user, by tool automation, or by both.

Abstract: One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.