Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

Abstract: Control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels.