Patents by Inventor Yee Chong Wong

Yee Chong Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double-layered low dielectric constant dielectric dual damascene method
    Patent number: 6803314
    Abstract: A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: October 12, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shyue Fong Quek, Ting Cheong Ang, Yee Chong Wong, Sang Yee Long
  • Double-layered low dielectric constant dielectric dual damascene method
    Publication number: 20020160604
    Abstract: A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer.
    Type: Application
    Filed: April 30, 2001
    Publication date: October 31, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shyue Fong Quek, Ting Cheong Ang, Yee Chong Wong, Sang Yee Leong
  • Triple-layered low dielectric constant dielectric dual damascene approach
    Patent number: 6406994
    Abstract: A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ting Cheong Ang, Shyue Fong Quek, Yee Chong Wong, Sang Yee Loong