Abstract: The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.

Abstract: The present invention is directed to a transmission line assembly and method of propagating signals therethrough that features forming transmission lines of the assembly to provide desired filtering properties. To that end, the assembly includes a plurality of spaced-apart transmission lines placing first and second sets of active circuits in electrical communication, with a subset of the plurality of spaced apart transmission lines having dimensions to filter unwanted characteristics of signals, propagating between the first and second sets and inductively coupled between one or more of the plurality of spaced-apart transmission lines. The method performs the function of the assembly.

Abstract: The embodiments of the present invention provide methods for choosing a via layout pattern(s) for power distribution network in a package for a semiconductor die. The chosen via layout pattern allows the power distribution network to meet the limitation on the loop inductance in order to avoid causing a large ?V affecting the functionality of semiconductor devices on the die. In addition, the chosen via layout pattern also meets the limitation of total number of vias allowed for the power distribution network in the package.