Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.

Abstract: According to one embodiment of the present invention, a substrate arrangement is provided. The substrate arrangement includes a first substrate; a second substrate positioned above the first substrate, the second substrate comprising a first through hole; a third substrate positioned above the second substrate, the third substrate comprising a second through hole; a first electrically conductive interconnect pillar positioned on the first substrate and extending from the first substrate through the first through hole to electrically contact the third substrate; and a second electrically conductive interconnect pillar positioned on the second substrate and extending from the second substrate through the second through hole. A method of manufacturing a substrate arrangement is also provided.