Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.