Abstract: An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (??) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

Abstract: An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (??) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

Abstract: Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.