Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

Abstract: A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

Abstract: A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.

Abstract: A repairable multi-layer memory chip stack is provided. Each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.

Abstract: A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments.