Patents by Inventor Yee-Wing Hsieh

Yee-Wing Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for generating design constraints
    Patent number: 8627249
    Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Marcalo Glusman, Angela Krstic, Yee-Wing Hsieh, Andy Lin
  • Verifying multiple constraints for circuit designs
    Patent number: 8209648
    Abstract: Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: June 26, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shan-Chyun Ku, Marcelo Glusman, Yee-Wing Hsieh, Manish Pandey, Angela Krstic, Sarath Kirihennedige
  • Method and system for generating design constraints
    Patent number: 7962886
    Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: June 14, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Marcelo Glusman, Angela Krstic, Yee-Wing Hsieh, Andy Lin