Patents by Inventor Yeh-Chi Hsu
Yeh-Chi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220359364Abstract: A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.Type: ApplicationFiled: March 16, 2022Publication date: November 10, 2022Applicant: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Gao-Tian Lin
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Patent number: 10756077Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.Type: GrantFiled: December 14, 2017Date of Patent: August 25, 2020Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
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Patent number: 10504847Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.Type: GrantFiled: December 14, 2017Date of Patent: December 10, 2019Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
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Publication number: 20190139898Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.Type: ApplicationFiled: December 14, 2017Publication date: May 9, 2019Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
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Publication number: 20190139952Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.Type: ApplicationFiled: December 14, 2017Publication date: May 9, 2019Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
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Patent number: 10204852Abstract: A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.Type: GrantFiled: February 3, 2017Date of Patent: February 12, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Yeh-Chi Hsu, Chen-Yueh Kung
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Publication number: 20170148720Abstract: A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: Yeh-Chi HSU, Chen-Yueh KUNG
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Patent number: 9601425Abstract: The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.Type: GrantFiled: August 18, 2015Date of Patent: March 21, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Yeh-Chi Hsu, Chen-Yueh Kung
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Patent number: 9418964Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.Type: GrantFiled: March 26, 2012Date of Patent: August 16, 2016Assignee: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Wei-Chih Lai
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Publication number: 20160126175Abstract: The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.Type: ApplicationFiled: August 18, 2015Publication date: May 5, 2016Inventors: Yeh-Chi HSU, Chen-Yueh KUNG
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Patent number: 8796848Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.Type: GrantFiled: January 11, 2011Date of Patent: August 5, 2014Assignee: Via Technologies, Inc.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu
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Patent number: 8736079Abstract: A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.Type: GrantFiled: July 26, 2011Date of Patent: May 27, 2014Assignee: VIA Technologies, Inc.Inventors: Yu-Kai Chen, Yeh-Chi Hsu
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Patent number: 8698325Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.Type: GrantFiled: March 17, 2011Date of Patent: April 15, 2014Assignee: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Yu-Kai Chen, Yeh-Chi Hsu, Ying-Ni Lee, Wei-Chih Lai
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Publication number: 20130175681Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.Type: ApplicationFiled: March 26, 2012Publication date: July 11, 2013Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Wei-Chih Lai
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Publication number: 20120299192Abstract: A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.Type: ApplicationFiled: July 26, 2011Publication date: November 29, 2012Applicant: VIA TECHNOLOGIES, INC.Inventors: Yu-Kai Chen, Yeh-Chi Hsu
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Publication number: 20120098125Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.Type: ApplicationFiled: March 17, 2011Publication date: April 26, 2012Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yuan Chang, Yu-Kai Chen, Yeh-Chi Hsu, Ying-Ni Lee, Wei-Chih Lai
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Publication number: 20110108984Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.Type: ApplicationFiled: January 11, 2011Publication date: May 12, 2011Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu
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Patent number: 7906377Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.Type: GrantFiled: April 29, 2009Date of Patent: March 15, 2011Assignee: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu
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Publication number: 20100155939Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.Type: ApplicationFiled: April 29, 2009Publication date: June 24, 2010Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu