Patents by Inventor Yeh-Jye Wang

Yeh-Jye Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for optimizing die placement
    Patent number: 7353077
    Abstract: A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 1, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chih-Wei Lin, Hong-Hsing Chou, Yeh-Jye Wang, Chen-Fu Chien, Jen-Hsin Wang, Chih-Wei Hsiao
  • Methods for optimizing die placement
    Publication number: 20070027567
    Abstract: A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
    Type: Application
    Filed: September 8, 2005
    Publication date: February 1, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Hong-Hsing Chou, Yeh-Jye Wang, Chen-Fu Chien, Jen-Hsin Wang, Chih-Wei Hsiao