Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.

Abstract: The invention advantageously provides a novel method for making self-aligned contacts on a semiconductor substrate. A gate electrode having a vertical sidewall and a protecting layer thereon is formed over the semiconductor substrate. A doped region is formed in the substrate adjacent to the gate electrode. An insulating sidewall spacer is formed on the sidewall of the gate electrode. A second doped region is formed in the substrate adjacent to the sidewall spacer. A second protecting layer is formed to cover or blanket the first protecting layer, the sidewall spacer, and the substrate. An interlayer insulting layer is provided on the second protecting layer in order to form a planer surface. The interlayer insulating layer and the second protecting layer are etched to expose the doped regions to form the self-aligned contacts.

Abstract: The intrinsic refresh time of a DRAM and the reliability of the gate oxide of the pass transistor of the memory cell of the DRAM is improved by a method to form electronic components of an integrated circuit on a semiconductor substrate that will eliminate damage to molecular bonds and reduce junction leakage within the semiconductor substrate. The method begins by forming said electronic components using recognized methods to create implantations, insulating oxide layers, selectively etching the insulating oxide layers and deposited conductive layers to assemble the transistors and capacitors of the integrated circuit. Interconnections between the electronic components are then formed. The interconnections include multiple layers of metal, multiple layers of heavily doped polycrystalline silicon, and silicon/metal alloys to connect terminals of said electronic components to the multiple layers of metals and multiple layers of heavily doped polycrystalline silicon.

Abstract: A dielectric layer is deposited over an etching stop layer. Then, a photoresist pattern is patterned on the dielectric layer. An anisotropical etching is performed to etch the dielectric layer by using the photoresist pattern as an etching mask to generate a slot in the dielectric layer. An isotropical etching is subsequently performed using the photoresist pattern as an etching mask. A further anisotropical etching is used to create contact holes to the substrate. Then, the photoresist pattern is stripped. A conductive layer is deposited along the surface of the etched dielectric layer and on the side walls of the contact holes. A filling material is refilled into the cup-shape cavities. The upper portion of the conductive layer is left exposed by the filling material. A selective etching step is performed to remove the upper portions of the conductive layer by using the filling material as a mask. The filling material and the etched dielectric layer are removed.

Abstract: The present invention discloses a method for eliminating leakage current in a semiconductor device by preventing silicon loss in a first area of a substrate during fabricating the semiconductor device. The method according to the preferred embodiment of the present invention includes the following steps. Firstly, form a first gate structure on a second area of the substrate, and form a first structure together with a second structure on the first area of the substrate. Then form a dielectric layer on the topography of the wafer. Next, etch a thickness of the dielectric layer until about 200-1000 angstroms in thickness of the dielectric layer is remained. Subsequently, form a photoresist pattern on the first area of the substrate, and etch the exposed second portion of the dielectric layer to form spacers of the first gate structure. The spacers and the gate structure constitute a gate electrode of a first transistor.

Abstract: A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist shape, to be used as an etch mask, during the patterning of the straight walled, silicon nitride capped, gate structure. A silicon oxynitride layer, with a specific thickness range between about 820 to 920 Angstroms, is used as a bottom anti-reflective coating, (BARC), layer, located between an overlying straight walled, photoresist shape, and an underlying silicon nitride capping layer. The BARC layer retards the reflection emitted from a silicon nitride capping layer, during the photolithographic exposure procedure, used for definition of the straight walled, photoresist shape, allowing the desired straight walled, photoresist shape, to be obtained, independent of the thickness of the silicon nitride capping layer.

Abstract: This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.

Abstract: A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched to form a node structure. A non-conformal oxide is formed on the node structure so that the non-conformal oxide has an overhang portion and a lower portion on the sidewall of the node structure. The non-conformal oxide is isotropically etched to remove the lower portion of the non-conformal oxide and to expose the lower sidewall of the node structure. A second conductive layer is conformally deposited on the non-conformal oxide layer and the lower sidewall of the node structure. The second conductive layer is anisotropically etched, using the overhang portion of the non-conformal oxide as a mask. Then the non-conformal oxide is removed by using a highly selective etching process.

Abstract: A crown-shape capacitor node is formed using a tapered etching process to increase the capacitance of the capacitor. A doped polysilicon layer is deposited over a substrate from which the capacitor node is formed. A tapered trench is formed in a doped polysilicon layer using a mask layer. The mask layer is removed and a dielectric layer is deposited over the doped polysilicon layer and filling the tapered trench. The dielectric layer is then etched back, leaving residual portions in the tapered trench. The doped polysilicon layer is then etched using the dielectric material in the tapered trench as an etching mask. The resulting capacitor node has tapered sidewalls, which increases the surface area of the capacitor node, thereby increasing the capacitor's capacitance. The mask layer can be formed so that the tapered etching process forms the capacitor node with either tapered exterior sidewalls or a tapered trench.

Abstract: A new method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device is described. Semiconductor device structures are formed in and on a semiconductor substrate. A dielectric layer is deposited overlying the semiconductor device structures. The dielectric layer is covered with a photoresist mask and partially etched into to form first openings of a first width wherein the first openings do not contact the underlying semiconductor device structures. An oxide layer is deposited over the dielectric layer and within the first openings whereby second openings are formed having a second width smaller than the first width. The oxide layer is etched away whereby the second openings are extended through the dielectric layer to the underlying semiconductor device structures to form small contact openings having the second width and whereby the dielectric layer is planarized.