Abstract: A high speed data network having a novel data translator having an SRAM data buffer in the full to half duplex direction and flow control media access elements, such as for detecting data collision and retransmission of data, for providing transparent high data rate transfer between full and half duplex data media. The main SRAM data buffer provides multiple frame FIFO storage and configured to provide alternating incoming and outgoing data access. The preferred embodiment further includes main SRAM incoming FIFO and outgoing FIFO memories. The outgoing FIFO memory is configured to operate in an alternating in/out memory access (independent of the main SRAM incoming and outgoing data access) providing data byte access after the byte is written from the main SRAM. Furthermore, the outgoing FIFO memory supplies the data to be retransmitted in the event of a data collision, without interrupting the operation(s) of the main SRAM buffer.