Abstract: The present disclosure discloses a method for performing a matrix multiplication on an on-chip system and related products. The on-chip system is included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus.

Abstract: An integrated circuit apparatus may be included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus may further include an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. The solution of the present disclosure may reduce the amount of data transferred between an internal device and an external storage apparatus, thus minimizing the I/O bottleneck caused by bandwidth limitations and then improving the overall performance of the integrated circuit apparatus.

Abstract: The present disclosure provides a neural network model splitting method and related products. The scheme provided by the present disclosure splits an operator into a plurality of smaller-scale sub-operators, so that a compute library under a single-core architecture can be called directly, which helps to avoid the extra work caused by re-implementation.