Patents by Inventor Yehea I Ismail

Yehea I Ismail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single-stage and multi-stage low power interconnect architectures
    Patent number: 7190286
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventors: Maged M. Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz, Yiben Ye, Vivek K. De, Yehea I. Ismail
  • Single-stage and multi-stage low power interconnect architectures
    Patent number: 6992603
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Maged M. Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz, Yiben Ye, Vivek K. De, Yehea I Ismail
  • Efficient model order reduction via multi-point moment matching
    Patent number: 6789237
    Abstract: A method for mapping moments in a reduced order system of approximation order q for use in simulating a circuit or system having n state variables at n nodes, the circuit or system having I inputs. The method includes calculating only q+I moments, where q is the approximation order and I is the number of inputs of the circuit or system being simulated, sorting the state variables at the n nodes, selecting q nodes of the n nodes, and calculating the dominate poles and zeros using a multi-point moment matching algorithm to simultaneously match q+I moments at the selected q nodes of the circuit or system. In one embodiment, the method includes using extra dummy inputs such that the total number of inputs equals I, such that K*I>q where K is a constant having a value in the range of about 4 to 8.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 7, 2004
    Assignee: Northwestern University
    Inventor: Yehea I. Ismail