Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.

Abstract: A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For one embodiment of the invention a portion of a datastream is received to a stream buffer. A data stream window is then created from the received portion, the data stream window containing data of more than one protocol. A corresponding portion of the data of a same protocol, is accessed through each of a plurality of processing machines. The accessed data is concurrently processed at each of the processing machines.

Abstract: A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.

Abstract: A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For one embodiment of the invention a portion of a datastream is received to a stream buffer. A data stream window is then created from the received portion, the data stream window containing data of more than one protocol. A corresponding portion of the data of a same protocol, is accessed through each of a plurality of processing machines. The accessed data is concurrently processed at each of the processing machines.