Abstract: A novel and useful mechanism of synchronizing and aligning a plurality of data streams. The invention comprises a plurality of sync machines and an alignment circuit which in combination function to synchronize and align multiple variable length cell streams. Each sync machine is operative to control the output clocking of a corresponding FIFO queue. The data stream output of each FIFO queue is monitored by a sync machine and all the sync machines are coupled to the alignment circuit. In operation, the sync machines synchronize to the cells by searching for the error checks sequence (ECS) at the end of each cell. Upon synchronization being achieved for all the data streams, the alignment circuit causes each sync machine to freeze its respective FIFO until the ECS arrives on the data stream most delayed in time. Once the ECS is received on the slowest data stream, the alignment circuit releases the hold and consequently the FIFOs are released by the sync machines.

Abstract: A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

Abstract: An arbiter utilizing a link list to arbitrate access between multiple data sources and a single destination. The arbiter is of the least recently used type whereby the data source that has not sent data for the longest time is given the highest priority. The arbiter provides an arbitration function in a simple manner and at high speeds. The arbiter utilizes a Non Empty Source Queue (NESQ) list that comprises only sources that are non empty, i.e., that have data ready to send. If a source queue chosen for data transmission still has data to send, it is placed at the end of the NESQ list. When a source queue becomes empty after the transmission of data, the source index is removed from the linked list. Conversely, when a source queue that was previously empty receives a new packet it is added to the end of the linked list.

Abstract: An apparatus for and a method of reducing the packet length count processing of data packets in a network device. The apparatus and method determine the length and end of a packet at the ingress point of the network computing device, e.g., a switch or router, using a single counting function. After the counting function verifies the length of the data packet, a signal indicating the length of a data packet is generated. This packet length indicator signal is then propagated throughout the system along with the data packet itself. The packet length indicator signal is then used at all decision points that involve the data packet. The packet length indicator signal itself is generated so as to indicate the beginning of the start of the data packet in addition to the end of the data packet, thus indicating the length of the packet. This obviates the need for the length of the packet to be counted over and over again in the course of processing the data packet within the switch or router.