Patents by Inventor Yehuda Rosenblatt

Yehuda Rosenblatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060193354
    Abstract: An optical lasing device, comprising (i) a lasing medium disposed in a lasing cavity, (ii) an etalon disposed within the lasing cavity, and (iii) an electrically tuned filter device, such as a grating waveguide structure device. The lasing device also comprises a detector for determining the lasing power of the lasing device, and a controllable phase shift capability, and the device is preferably locked to a maximum of the lasing power by adjusting the phase, thereby achieving locking to a wavelength predetermined by the etalon, aligned to an ITU grid wavelength. Adjusting the phase shift to achieve the maximum of the lasing power is preferably performed using a closed loop system. Furthermore, adjusting of the phase shift to achieve a maximum of the lasing power is preferably also operative to wave lock the lasing device to a peak wavelength of the etalon.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 31, 2006
    Inventor: Yehuda Rosenblatt
  • Publication number: 20020096760
    Abstract: A method of forming a side access layer on a semiconductor chip, or especially a stack of semiconductor chips, is provided. A region of protective insulating material and one or more conductive pads are formed above a major surface of each chip substrate. Each conductive pad is located at least a certain height above the major surface of the substrate and at least a certain distance away from a side surface of the chip, with the region of protective material generally extending between each conductive pad and the major surface of the substrate. The insulating material thereby protects each conductive pad during subsequent etching of the side surface of each chip substrate. The edge of each conductive pad is then exposed, preferably by planarizing the side surface of the chip or stack. Also, a side interconnect layer may be formed on the side surface of the chip or stack to provide an electrical connection to each conductive pad.
    Type: Application
    Filed: January 24, 2001
    Publication date: July 25, 2002
    Inventors: Gregory Simelgor, Yehuda Rosenblatt