Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A method for ensuring CRC error generation by a data communication station after a transmitter exception such as an underrun whereby a parity bit is preset to a binary one, and toggled in response to successive binary ones of a serial bit stream. Each byte of the serial bit stream is transmitted sequentially. If a transmitter exception occurs, the byte before the exception is transmitted normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte, ensuring odd parity for the previous bit stream. Thereafter, a byte even parity is sent to assure that the overall message has odd parity. A receiving station interprets two consecutive bytes having the predetermined data pattern as the CRC, thus ensuring that the receiving station will reject the frame.

Abstract: A time slot assigner (20) for a serial communication system utilizes an encoded field of data. The time slot assigner (20) has a memory (52) for storing encoded data, a digital counter (60), a prescaler (62), a dedicated latch (58), and a time slot control logic (56). The enclosed data is partitioned into encoded data fields within the memory. A first encoded data field is utilized to indicate a last (LST) encoded data entry of a plurality of entries in the memory to be processed collectively, a second encoded data field (BRS) indicates a bit resolution of the data, a third encoded data field contains a count (CNT) value, and a fourth encoded data field selects a serial communication channel (CSEL). The time slot assigner (20) is activated by an active strobe start cycle signal, and is deactivated in response to a predetermined activated encoded data field.

Abstract: A voltage spike detection circuit for use in detecting clock edge transitions utilizes a voltage change detection circuit (16) and a voltage spike latching circuit (18). The voltage change detection circuit (16) provides an output pulse in response to each edge transition of a serial communication clock, including an edge caused by a noise spike on the serial communication clock. In response to receiving the output pulse of the voltage change detection circuit (16), the voltage spike latching circuit (18) provides an active system interrupt signal to a serial communication system. When the serial communication system receives the active system interrupt signal, the serial communication system momentarily activates a system reset signal and re-communicates the serial communication data.