Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Abstract: An encoding system (400) receives samples and coefficients from a bus (422). The system comprises a plurality of parallel operating memory devices (430-k), registers (435-k), computing units (440-k), and accumulator units (460-k). The system (400) further comprises a parallel-to-serial buffer (470) coupled to the accumulator units (440-k) and a pair generator (480) for providing amplitude/index pairs. The system (400) performs encoding steps such as transforming, quantizing, zigzagging, rate controlling, and run-length coding. Transforming is explained for the example of a Forward Discrete Cosine Transformation (FDCT). According to a method (500) of the present invention, zigzagging (510) occurs prior to transforming (570) and performed only once when transformation coefficients are provided to the memory devices (430-k) in a zigzag arrangement. Quantizing occurs prior to transforming by pre-calculating the coefficients with quantizers.

Abstract: A transfer layer of an ATM type used between a switch (216) and a number N of communication channels (218). Each communication channel (218) has second storage arrangement B.sub.0, . . . , B.sub.N-1 for storing cell queues having a length of up to P cells each, one of the second storage arrangements being in a busy condition if a minimum number M of cells is stored therein, where M is lesser of equal P. Each communication channel is assigned to one of the switch queues. The transfer layer (217) has third storage arrangement T for storage of a cell queue having a length of up to L cells. Furthermore the transfer layer (217) selectively disables the input of a cell from one of the switch queues into the third storage arrangement if the second storage arrangement is in a busy condition.

Abstract: An asynchronous transfer mode (ATM) system has a plurality of physical layers (24, 50, 52, and 26) coupled to one ATM layer (12) for communicating ATM data cells. In order to allow bi-directional communication, both the receive interface and the transmit interface of FIGS. 14 and 15 are coupled between the ATM layer and each physical (PHY) layer in the plurality of physical layers. In order to identify which physical layer of the plurality of physical layers is to either receive or transmit a data cell, a physical layer ID byte is transmitted along with the UTOPIA protocol multi-byte ATM data cell to address one physical layer in the plurality of physical layers.