Abstract: A method for forming one or more redundant vias (38a-38x) around a critical via (36) involves providing an integrated circuit design file (12) containing several overlay layers. Critical vias in the file (12) are identified via a step (16). Several redundant vias are serially placed around and connected in parallel to the critical via (36), and design rules are checked for each redundant via by performing steps (24-30). Redundant vias which do not violate design rules (26) are kept in a separate redundant overlay layer and added to the design of the integrated circuit. The added redundant vias increase the yield of the integrated circuit by bolstering the integrity of critical via connections.

Abstract: A mantissa addition system (2) having a mantissa adder (6) for adding two mantissas provides an addition result a plurality of bits arranged in sub-groups. The mantissa addition system also has a flag generator which generates a flag for each sub-group: each flag having an active state when all the bits in the respective sub-group are zero and an inactive state when at least one of the bits in the respective sub-group is non-zero. A first detector (46) determines the most significant flag that has the inactive state and provides a first control signal representative of the detected most significant flag. A first shifter (40) shifts the groups of bits of the addition result in response to the first control signal so that the sub-group of bits corresponding to the detected most significant flag is the most significant group.

Abstract: An exponent subtractor system (226) for a floating point adder (200) generates an exponent result (EXP.sub.-- low) and a rounded exponent result (EXP.sub.-- high) for an addition operation performed on two floating point numbers and generates overflow (Overflow.sub.-- low, Overflow.sub.-- high) and underflow flags (Underflow.sub.-- low, Underflow.sub.-- high) for the exponent result and the rounded exponent result before the completion of the updating of the exponent result in an exponent subtractor (52, 72).

Abstract: A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal.