Abstract: A semiconductor device includes an extension structure including a first horizontal conductive line extension, a first interlayer insulating layer, a second horizontal conductive line extension, and a second interlayer insulating layer stacked on a substrate and extending in a first horizontal direction, a first contact configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension, and the first interlayer insulating layer and contact the first horizontal conductive line extension, a second contact configured to pass through the second interlayer insulating layer and contact the second horizontal conductive line extension, and a first contact spacer extending between a sidewall of the first contact and the extension structure and configured to electrically isolate the first contact from the second horizontal conductive line extension.

Abstract: A semiconductor device includes a substrate, a data storage structure on the substrate, an insulating structure spaced apart from the data storage structure on the substrate, conductive lines spaced apart from each other and stacked in a vertical direction between the data storage structure and the insulating structure, active layers spaced apart from each other and stacked in the vertical direction between the data storage structure and the insulating structure, and intersecting the conductive lines, and a conductive pattern between the insulating structure and the active layers, and electrically connected to the active layers. The insulating structure includes first insulating patterns spaced apart from each other in a first horizontal direction, and a second insulating pattern between the first insulating patterns. The conductive pattern is between the second insulating pattern and the active layers. The second insulating pattern includes a material different from that of the first insulating patterns.

Abstract: A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.