Abstract: A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Abstract: A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Abstract: An embedded magnet frame, an integrated structure and a manufacturing method are disclosed. The manufacturing method includes: manufacturing conductive metal columns, a first sacrificial block and a second sacrificial block on a surface of a bearing plate; laminating a first dielectric layer on the surface of the bearing plate so that the first dielectric layer covers the conductive metal columns, the first sacrificial block and the second sacrificial block; thinning the first dielectric layer to expose surfaces of the conductive metal columns, the first sacrificial block and the second sacrificial block; etching the first sacrificial block and the second sacrificial block to form corresponding first and second mounting cavities, the second mounting cavity being used for mounting a chip; filling the first mounting cavity with magnetic slurry to form an embedded magnet; and removing the bearing plate to form an embedded magnet frame.

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

Abstract: A method for manufacturing embedded device packaging substrate, a packaging substrate, and a semiconductor are disclosed. The method includes: forming a first circuit layer; laminating a first photosensitive layer onto the first circuit layer; providing an embedded device on the first photosensitive layer, with a pin face of the embedded device facing away from the first photosensitive layer; providing a second photosensitive layer covering the embedded device; partially removing the first dielectric layer such that a minimum thickness of the first dielectric layer covering a side surface of the embedded device is greater than or equal to a preset threshold; providing a second dielectric layer covering the first dielectric layer; and forming, on the second dielectric layer, a second circuit layer that is electrically connected to the first circuit layer and the embedded device.

Abstract: An embedded device package substrate includes a line board including a first insulating layer and a first line layer located on an upper surface of the first insulating layer, a core layer covering the first line layer and including a preset opening, a device embedded in the preset opening, a packaging layer covering the core layer and filling the gap between the core layer and the device, and an outer line layer located on the packaging layer. The outer line layer is connected to a terminal of the device by a first conductive column penetrating through the packaging layer and to the first line layer by a second conductive column penetrating through the core layer and the packaging layer.

Abstract: A substrate manufacturing method, an embedded substrate and a semiconductor are disclosed. The method includes: manufacturing a first semi-finished substrate including first circuit layers and a first dielectric layer arranged in staggered and laminated manner; arranging a viscous material layer on the first circuit layer to form a device adhering area; adhering an embedded device on the device adhering area, a pin face of the embedded device facing away from the viscous material layer; laminating a second dielectric layer on the first circuit layer, which covers the viscous material layer and the embedded device; manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, the first conductive pillar extending through the second dielectric layer and configured for connecting the second circuit layer with the first circuit layer, the second conductive pillar being configured for connecting the embedded device with the second circuit layer.

Abstract: Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.

Abstract: A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.

Abstract: A chip high-density interconnection package structure includes a plate having a groove and a glass frame, a first via post penetrating the glass frame, a second via post penetrating the groove, a first line layer and a second line layer on the glass frame and electrically connected via the first via post, a third line layer and a fourth line layer on the groove and electrically connected via the second via post, a chip connection bridge on the third line layer in the groove, and a fifth line layer on the first line layer, and chips on the second line layer and the fourth line layer. The chip connection bridge has a first pad connected to the third line layer, the terminals of the two chips are connected to the fourth line layer and/or the second line layer, and the fifth line layer is connected to the first line layer.

Abstract: A method for manufacturing a device embedded packaging structure include laminating a first dielectric material on a copper foil to form a first dielectric layer, and forming a first feature pattern in the first dielectric layer to expose the copper foil, etching the exposed copper foil to form a device opening frame and a via post opening frame to obtain a metal frame, applying an adhesive layer on the metal frame, and mounting a device to the adhesive layer in the device opening frame, laminating a second dielectric material to form a second dielectric layer covering the metal frame and filling the device opening frame and the via post opening frame, forming a via post in the via post opening frame, and forming a first wiring layer and a second wiring layer conductively connected by the via post on the upper and lower surfaces of the second dielectric layer.

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

Abstract: A multichip interconnecting packaging structure includes a glass frame, a first line layer and a second line layer respectively provided on the first surface and the second surface of the glass frame, a first via post penetrating through the glass frame, a cavity penetrating through the glass frame, a chip connecting device embedded in the cavity, a first insulating layer filling the cavity to cover the chip connecting device, and a first chip and a second chip provided on the surface of the first line layer, wherein a terminal of the chip connecting device is connected to the first line layer, the first line layer and the second line layer are in conductive communication through the first via post, the first chip and the second chip are connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip.

Abstract: A packaging structure for realizing chip interconnection includes a core layer, a bridging layer, a first dielectric layer, a second dielectric layer, a first bonding pad layer and a second bonding pad layer. The first dielectric layer is arranged between the core layer and the first bonding pad layer, the second dielectric layer is arranged between the second bonding pad layer and the core layer. The first bonding pad layer is connected with the core layer through a first via, the second bonding pad layer is connected with the core layer through a second via. The bridging layer is embedded in the first dielectric layer. The bridging layer is electrically insulated from the core layer, and the bridging layer is connected with the first bonding pad layer through a third via.

Abstract: A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Abstract: A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

Abstract: A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.

Abstract: A connector for implementing multi-faceted interconnection according to an embodiment of the present disclosure includes a first dielectric layer between a first circuit layer and a second circuit layer, a first copper pillar layer connecting the first circuit layer and the second circuit layer in the first dielectric layer, a second dielectric layer on the first circuit layer, a third circuit layer on the second dielectric layer, and a vertical second copper pillar layer connected to the third circuit layer, wherein an opening is formed in the second dielectric layer to expose the first circuit layer, and the second copper pillar layer exposes side faces facing side end faces of the first dielectric layer and the second dielectric layer.