Patents by Inventor Yelehanka R. Pradeep

Yelehanka R. Pradeep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6277716
    Abstract: A method of fabricating a gate stack having an endpoint detect layer and a multi-step etch process to prevent damage to a gate dielectric layer. The special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon to oxide ratio to prevent damage to the gate oxide layer. The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode. We etch the gate stack and the endpoint detect layer using a multi-step etch comprising at least 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: August 21, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vijaikumar Chhagan, Yelehanka R. Pradeep, Tjin Tjin Tjoa